1. Field of the Invention
The present invention relates to a surface emitting semiconductor laser suitably used for optical interconnections and optical information processing, and more particularly, to a structure directed to reducing the resistance of the surface emitting semiconductor laser.
2. Description of the Related Art
Recently, large-capacity, high-speed optical communications networks such as WDM (Wavelength Division Multiplexing) have rapidly been equipped along with an increased capacity and a wider band in data communications. High-speed, parallel-processing optical communication techniques have infiltrated even in short-distance communications such as Gigabit Ethernet or data links. In the twenty-first century in which optical communications support the social infrastructure, optical devices would play a more important role. Nowadays, semiconductor lasers are embedded, as optical sources, in equipment involved in optical communications, DVD players, CD players and laser printing machines.
These semiconductor lasers are of a type in which laser light is emitted from the cleaved edge of the semiconductor substrate. This type of laser is called edge-emission laser. In contrast, there is another type of laser called vertical cavity surface emitting laser diode (VCSEL) that has a resonator arranged vertical to the surface of the semiconductor substrate and emits laser light from the semiconductor surface. VCSEL has a light emission aperture formed on the wafer surface by photolithography, which is one of the conventional semiconductor processes. Thus, VCSEL easily realizes a two-dimensional array and a large-scale device, which cannot be accomplished by the edge-emission type. In addition, VCSEL has a small volume of the active layer, so that it needs a small drive current and consumes a small amount of power. Further, VCSEL can be driven fast and needs a compact optical system because it has a complete round beam profile. These features are not provided by the edge-emission laser. Furthermore, VCSEL has some advantages in the fabrication process. For instance, VCSEL can be tested on the wafer and does not need the cleaved edges, on the device, this improving the yield.
Pioneering research of VCSEL was done by, for example, K. Iga (see K. Iga, “SURFACE EMITTING LASER”, IEICE Transactions C-1, 1998 September, Vol. J81-C-1, No. 9, p.483–493. FIG. 9 shows a recent structure of VCSEL, which has a resonator 602 formed in the direction vertical to the horizontal surface of a semiconductor substrate 601. The resonator 602 has an active layer 603, a lower reflection mirror 604, an upper reflection mirror 605, and a spacer layer 606. The active layer 603 confines carriers and creates light. Each of the mirrors 604 and 605 is formed by a respective laminate of semiconductor layers. The spacer layer 606 matches the phase emitted from the active layer 603 at ends of the reflection mirrors 604 and 605. An upper contact layer 607 is defined as a part of the upper reflection mirror 604. An upper electrode 608 is provided on an interlayer insulation film 610 having a portion provided on the upper contact layer 607. The upper electrode 608 has a laser emission aperture 611. A lower electrode 609 is provided on the back surface of the semiconductor substrate 601.
An oxidization method is the main stream approach for fabricating the current confinement function in VCSEL. The oxide-confined VCSEL has a mesa structure formed by dry etching the laminate of semiconductor layers on the semiconductor substrate 601. Then, a layer 612 that has a high Al composition ratio is steam-oxidized from the circumference of the mesa structure with moisture kept at a high temperature, this resulting in an insulation region 612A. At that time, the oxidizing time may be adjusted so that a semiconductor layer 612B that is an electrically conductive region remains in the center of the mesa and the current confining structure is defined. The current confining structure defined by the oxidized layer also functions to stabilize the transverse mode of laser light due to the difference in the refractive index between the circumferential insulation layer and the central semiconductor conduction region. The current confining layer is also referred to as oxide-confined aperture layer. As described in the following documents, the oxidization type VCSEL with the oxide-confined aperture layer has a small threshold current and a good current-light characteristic, as described in H. Otoma, “FABRICATION AND PERFORMANCE OF 12×12 MATRIX-ADDRESSED 780 nm OXIDE-CONFINED VCSEL ARRAY”, Bulletin of Solid State Physics and Applications, 1999, Vol. 5, No. 1, p. 11–15, and Nobuaki Ueki, “Single-Transverse-Mode 3.4-mW Emission of Oxide-confined 780-nm VCSEL's”, IEEE PHOTONICS TECHNOLOGY LETTERS, 1999 DECEMBER, Vol. 11, No. 12, p. 1539–1541.
The oxide-confined VCSEL has a much smaller volume of the active region than that of the conventional edge-emission semiconductor laser, and an index waveguide type laser, and is therefore characterized that it can operate at a rate of 10 Gb/s or higher (see J. Sakurai, “10 Gb/s Surface Emission Semiconductor Laser”, Electronic Materials, 2002 November, Vol. 41, No. 11, p. 49–52. The IEEE standardized the regulations of 10 Gigabit Ethernet as new regulations of high-speed local area network (LAN) on June, 2002. Most of the regulations chose 850 nm or 1310 nm VCSEL as the optical source. This explicitly shows that high-speed performance of VCSEL is attractive. There has considerable activity in the further development of improvements in the operating speed of VCSEL in order to making sure the firm position as the optical source of the communications infrastructure.
Improvements in the operating speed of VCSEL will be achieved by reducing the volume of the active layer as much as possible and reducing the resistance and capacitance of the VCSEL device. The volume of the active layer of the oxide-confined VCSEL is defined so that the carriers (holes) are confined in the small semiconductor region in the center of the mesa due to the oxide-confined aperture. At that time, current is generated so that the holes in the periphery of the mesa gather at the center of the mesa. The in-plane resistance that the carriers receive during traveling is one of the factors that increase the device resistance. Japanese Patent Application Publication No. 2002-185079 discloses a method for reducing the in-plane component of the hole resistance by providing a layer between the current confining layer and the second electrode, in which two-dimensional carriers are created.
On the other hand, long-distance communications need a single-mode VCSEL applicable to the single-mode optical fiber. Proposals described in the following papers would be effective to secure the stable single mode and obtain satisfactory optical output: Grabherr, “Efficient Single-Mode Oxide-Confined GaAs VCSEL's Emitting in the 850-nm Wavelength Regime”, IEEE PHOTONICS TECHNOLOGY LETTERS, 1997 OCTOBER, Vol. 9, No. 10, p. 1304–1306, or Aaron, “Aperture Placement Effects in Oxide-Defined Vertical-Cavity Surface-Emitting Lasers”, IEEE PHOTONICS TECHNOLOGY LETTERS, 1998 OCTOBER, Vol. 10, No. 10, p. 1362–1364. According to the proposals, the current confining layer in the semiconductor multilayer is provided in the vicinity of the position at which the electric field of the standing wave of laser light is minimized (at the node).
However, the conventional VCSEL has the following drawbacks. The structure proposed by Grabherr or Aaron will now be described in more detail with reference to FIGS. 10A and 10B. FIG. 10A shows a case whether an oxide-confined aperture 705 is positioned at the loop position at which the maximum electric field of a standing wave 713 of laser light is available. FIG. 10B shows another case where the oxide-confined aperture 705 is positioned at the node position at which the minimum electric field of the standing wave 713 is available. The VCSEL devices shown in FIGS. 10A and 10B has an n-type GaAs semiconductor layer 701 doped with Si (Nd=1×1018 cm−3), a distributed Bragg reflection (DBR) mirror layer 702 composed of n-type Al0.3Ga0.7As layers and n-type Al0.1Ga0.9As layers that are alternately laminated to a thickness of 40.5 periods, and an undoped λ Al0.2Ga0.8As spacer layer 703 where λ denotes the film thickness and its optical thickness is equal to the wavelength of laser light. A reference numeral 704 indicates a triple quantum well GaAs/Al0.15Ga0.85As active layer in the spacer layer, and a reference numeral 705 is an oxide-confined aperture of a p-type AlAs layer doped with Zn (Na=7×1017 cm−3) formed by oxidizing the circumferential periphery. Layers 703 and 704 form an active region 750. A reference numeral 706 indicates a p-type Al0.9Ga0.1As layer doped with Zn (Na=7×1017 cm−3), and a reference numeral 707 indicates a p-type Al0.3Ga0.1As layer doped with Zn (Na=1.5 ×1018 cm−3). One pair of layers 706 and 707 forms one period (λ/2) of the p-type DBR layer. A reference numeral 708 indicates a DBR layer composed of p-type Al0.3Ga0.7As layers doped with Zn (Na=7×1017 cm−3) and Al0.9Ga0.1 layers that form the laminate starting from the second layer. A reference numeral 709 indicates a p-type GaAs contact layer doped with Zn (Na=1×1019 cm−3), and a reference numeral 710 indicates an interlayer insulation film made of SiNx. A reference numeral 711 indicates a p-side electrode, and a reference numeral 712 indicates an n-side electrode.
In the structure shown in FIG. 10A, the undoped λ Al0.2Ga0.8As spacer layer 703 is formed just below the oxide-confined aperture layer 705 that is the current confining layer. Since the layer 703 is undoped, it has a large resistance. In contrast, the structure shown in FIG. 10B has the p-type Al0.9Ga0.1As layer 706 doped with Zn (Na=7×1017 cm−3) that has an Al composition ratio of 90% and is located just below the oxide-confined aperture 705. Originally, the semiconductor layer that has a high Al composition ratio has a low carrier mobility and a poor carrier density due to a low p-type impurity-activated ratio, and is thus a high-resistance layer. This high-resistance layer is operatively added to the current path that is narrowed due to the current confining layer. Thus, the presence of the high-resistance layer just below the oxide-confined aperture layer 705 increases the device resistance and prevents high-speed drive. Regarding this problem, Japanese Patent Application Publication No. 2002-185079 proposes to use the carrier generating layer between the current confining layer and the upper electrode. However, the proposed layer only reduces the resistance at the position at which the carriers travel towards the current confining layer.